1. Field of the Invention
The present invention is broadly concerned with novel compositions and methods of using those compositions to form bonding compositions that can support active wafers on a carrier wafer or substrate during wafer thinning and other processing.
2. Description of the Prior Art
Wafer (substrate) thinning has been used to dissipate heat and aid in the electrical operation of integrated circuits (IC). Thick substrates cause an increase in capacitance, requiring thicker transmission lines, and, in turn, a larger IC footprint. Substrate thinning increases impedance while capacitance decreases impedance, causing a reduction in transmission line thickness, and, in turn, a reduction in IC size. Thus, substrate thinning facilitates IC miniaturization.
Geometrical limitations are an additional incentive for substrate thinning. Via holes are etched on the backside of a substrate to facilitate frontside contacts. In order to construct a via using common dry-etch techniques, geometric restrictions apply. For substrate thicknesses of less than 100 μm, a via having a diameter of 30-70 μm is constructed using dry-etch methods that produce minimal post-etch residue within an acceptable time. For thick substrates, vias with larger diameters are needed. This requires longer dry-etch times and produces larger quantities of post-etch residue, thus significantly reducing throughput. Larger vias also require larger quantities of metallization, which is more costly. Therefore, for backside processing, thin substrates can be processed more quickly and at lower cost.
Thin substrates are also more easily cut and scribed into ICs. Thinner substrates have a smaller amount of material to penetrate and cut and therefore require less effort. No matter what method (sawing, scribe and break, or laser ablation) is used, ICs are easier to cut from thinner substrates. Most semiconductor wafers are thinned after frontside operations. For ease of handling, wafers are processed (i.e., frontside devices) at their normal full-size thicknesses, e.g., 600-700 μm. Once completed, they are thinned to thicknesses of 100-150 μm. In some cases (e.g., when hybrid substrates such as gallium arsenide (GaAs) are used for high-power devices) thicknesses may be taken down to 25 μm.
Mechanical substrate thinning is performed by bringing the wafer surface into contact with a hard and flat rotating horizontal platter that contains a liquid slurry. The slurry may contain abrasive media along with chemical etchants such as ammonia, fluoride, or combinations thereof. The abrasive provides “gross” substrate removal, i.e., thinning, while the etchant chemistry facilitates “polishing” at the submicron level. The wafer is maintained in contact with the media until an amount of substrate has been removed to achieve a targeted thickness.
For a wafer thickness of 300 μm or greater, the wafer is held in place with tooling that utilizes a vacuum chuck or some means of mechanical attachment. When wafer thickness is reduced to less than 300 μm, it becomes difficult or impossible to maintain control with regard to attachment and handling of the wafer during further thinning and processing. In some cases, mechanical devices may be made to attach and hold onto thinned wafers, however, they are subject to many problems, especially when processes may vary. For this reason, the wafers (“active” wafers) are mounted onto a separate rigid (carrier) substrate or wafer. This substrate becomes the holding platform for further thinning and post-thinning processing. Carrier substrates are composed of materials such as sapphire, quartz, certain glasses, and silicon, and usually exhibit a thickness of 1000 μm. Substrate choice will depend on how closely matched the coefficient of thermal expansion (CTE) is between each material. However, most of the currently available adhesion methods do not have adequate thermal or mechanical stability to withstand the high temperatures encountered in backside processing steps, such as metallization or dielectric deposition and annealing. Many current methods also have poor planarity (which contributes excessive total thickness variation across the wafer dimensions), and poor chemical resistance.
One method that has been used to mount an active wafer to a carrier substrate is via a thermal release adhesive tape. This process has two major shortcomings. First, the tapes have limited thickness uniformity across the active wafer/carrier substrate interface, and this limited uniformity is often inadequate for ultra-thin wafer handling. Second, the thermal release adhesive softens at such low temperatures that the bonded wafer/carrier substrate stack cannot withstand many typical wafer processing steps that are carried out at higher temperatures.
Thermally stable adhesives, on the other hand, often require excessively high bonding pressures or bonding temperatures to achieve sufficient melt flow for good bond formation to occur. Likewise, too much mechanical force may be needed to separate the active wafer and carrier wafer because the adhesive viscosity remains too high at practical debonding temperatures. Thermally stable adhesives can also be difficult to remove without leaving residues.
There is a need for new compositions and methods of adhering an active wafer to a carrier substrate that can endure high processing temperatures and that allow for ready separation of the wafer and substrate at the appropriate stage of the process.